1. Field of the Invention
Generally, the present disclosure relates to microstructures, such as advanced integrated circuits, and, more particularly, to metallization systems comprising sophisticated dielectric and conductive materials.
2. Description of the Related Art
In the field of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep submicron range, thereby increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of functions. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect structures electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect structures are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area as typically the number of interconnections required increases more rapidly than the number of circuit elements. Thus, usually a plurality of stacked wiring layers, also referred to as metallization layers, is provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. The vertical connections and the metal lines may also commonly be referred to as interconnect structures. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect structures are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific ICs) and the like.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.05 μm and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm2 in the individual interconnect structures, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Consequently, well-established materials, such as aluminum, are being replaced by copper and copper alloys, i.e., materials with significantly lower electrical resistivity and improved resistance to electromigration even at considerably higher current densities compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials, which are typically used in combination with copper in order to reduce the parasitic capacitance within complex metallization layers. In order to provide the necessary adhesion and to avoid the undesired diffusion of copper atoms into sensitive device regions, it is, therefore, usually necessary to provide a barrier layer between the copper and the low-k dielectric material in which the copper-based interconnect structures are embedded. Although silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms, selecting silicon nitride as an interlayer dielectric material is less then desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitance of neighboring copper lines, which may result in non-tolerable signal propagation delays. Hence, a thin conductive barrier layer that also imparts the required mechanical stability to the copper is usually formed so as to separate the bulk copper from the surrounding dielectric material, thereby reducing copper diffusion into the dielectric materials and also reducing the diffusion of unwanted species, such as oxygen, fluorine and the like, into the copper. Furthermore, the conductive barrier layers may also form highly stable interfaces with the copper, thereby reducing the probability for significant material transport at the interface, which is typically a critical region in view of increased diffusion paths that may facilitate current-induced material diffusion. Currently, tantalum, titanium, tungsten and their compounds, with nitrogen and silicon and the like, are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of diffusion suppressing and adhesion properties.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first a dielectric layer is formed which is then patterned to include trenches and/or via openings which are subsequently filled with copper, wherein, as previously noted, prior to filling in the copper, a conductive barrier layer is formed on sidewalls of the trenches and vias. The deposition of the bulk copper material into the trenches and via openings is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.3 μm or even less in combination with trenches having a width ranging from 0.1 μm to several μm. Electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication. However, for the dimensions of the metal regions in semiconductor devices, the void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper-based interconnect structure significantly depend on process parameters, materials and geometry of the structure of interest. Since the geometry of interconnect structures is substantially determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and nonconductive barrier layers, the copper microstructure and the like, and their mutual interaction on the characteristics of the interconnect structure as a whole so as to insure both high yield and the required product reliability. In particular, it is important to identify, monitor and reduce degradation and failure mechanisms in metallization systems for various configurations so as to maintain device reliability for every new device generation or technology node.
Accordingly, a great deal of effort is being made in investigating the degradation of copper interconnects, especially in combination with low-k dielectric materials or ultra low-k (ULK) materials having a relative permittivity of 3.0 or even less, in order to find new materials and process strategies for forming copper-based lines and vias with a low overall permittivity and superior reliability.
One failure mechanism which is believed to significantly contribute to a premature device failure is the electromigration-induced material transport particularly along an interface formed between the copper and any barrier materials and a dielectric cap layer, which may be provided on the sidewalls and at the top of the core metal.
Consequently, the conductive barrier material may not only have to provide superior adhesion and copper diffusion blocking capabilities, but may also have to provide strong interfaces with the copper core metal in order to reduce the current-induced copper diffusion along the interface areas and also to substantially avoid material diffusion through any barrier layers. Upon further device scaling, in particular the characteristics of the conductive barrier materials may gain in importance since typically the thickness of the barrier materials may not scale in the same manner as the overall lateral dimensions of the interconnect structures have to be reduced. That is, in view of a reliable coverage of any inner surface areas of the interconnect structures, a certain minimum thickness may have to be preserved in order to reliably cover any critical sidewall areas, such as lower portions of via openings and the like. Consequently, the layer thickness may be significantly greater in less critical areas, thereby reducing the effective cross-sectional size of the resulting interconnect features. Hence, upon further scaling of the interconnect structure, the specific resistivity of these structures may increase due to a relative increase of the conductive barrier material with respect to the actual highly conductive core metal. For this reason, great efforts are being made in reducing the thickness of the conductive barrier layer systems while not unduly affecting the overall electromigration performance. It appears, however, that required electromigration behavior in combination with a desired low resistivity of the resulting interconnect structures may be difficult to achieve on the basis of well-established barrier layer systems comprising tantalum and tantalum nitride.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.